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  RTL Synthesis(Design Synthesis)培訓
   班級規模及環境--熱線:4008699035 手機:15921673576/13918613812( 微信同號)
       堅持小班授課,為保證培訓效果,增加互動環節,每期人數限3到5人。
現場面授
   上課時間和地點
上課地點:【上!浚和瑵髮W(滬西)/新城金郡商務樓(11號線白銀路站) 【深圳分部】:電影大廈(地鐵一號線大劇院站)/深圳大學成教院 【北京分部】:北京中山/福鑫大樓 【南京分部】:金港大廈(和燕路) 【武漢分部】:佳源大廈(高新二路) 【成都分部】:領館區1號(中和大道) 【沈陽分部】:沈陽理工大學/六宅臻品 【鄭州分部】:鄭州大學/錦華大廈 【石家莊分部】:河北科技大學/瑞景大廈 【廣州分部】:廣糧大廈 【西安分部】:協同大廈
近開課時間(周末班/連續班/晚班)
RTL Synthesis(Design Synthesis)培訓:2022年6月13日.(歡迎您垂詢,視教育質量為生命!)
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        專注高端培訓17年,曙海提供的課程得到本行業的廣泛認可,學員的能力
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   新優惠
       ◆在讀學生憑學生證,可優惠500元。

        本課程實戰演練使用Synopsys公司的DC,PT等工具,
和Cadence公司的Encounter,Virtuoso等工具,多工具聯合從頭至尾強化練習整個芯片的生成過程,強調實戰,實戰,還是實戰!

        免費、無保留贈送,教學過程中使用的Synopsys公司和Cadence公司的全套工具和安裝方法,而且還贈送已經在VMware Linux下安裝好的Synopsys公司和Cadence公司的全套工具(這套工具非常珍貴,費了老師很多心血才全部安裝好),讓您隨時隨地,打開電腦就能進行芯片的設計和練習!

IC工具虛擬機
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        3、培訓合格學員可享受免費推薦就業機會。

  RTL Synthesis(Design Synthesis)培訓
培訓方式以講課和實驗穿插進行

課程描述:

第一階段 Design Compiler 1

Overview
This course covers the ASIC synthesis flow using Design Compiler Topographical / Graphical -- from reading in an RTL design (Verilog, SystemVerilog and VHDL) to generating a final gate-level netlist. You will learn how to read in your design file(s), specify your libraries and physical data, constrain a complex design for timing and floorplan, apply synthesis techniques using Ultra, compile to achieve timing closure and an acceptable congestion, analyze the synthesis results for timing and congestion, and generate output data that works with downstream layout tools.

You will verify the logic equivalence of synthesis transformations (such as Datapath optimizations and Register Retiming) to that of an RTL design using Formality. The course includes labs to reinforce and practice key topics discussed in lecture. All the covered commands and flows are printed separately in a 5-page Job Aid, which you can refer to back at work.

Objectives
At the end of this workshop the student should be able to:
  • Create a setup file to specify the libraries and physical data
  • Read in a hierarchical design
  • Constrain a complex design for timing, taking into account different environmental attributes such as output loading, input drive strength, process, voltage and temperature variations, as well as post-layout effects such as clock skew
  • Constrain multiple (generated) clocks considering Signal integrity analysis
  • Execute the recommended synthesis techniques to achieve timing closure
  • Analyze and Improve global route congestion
  • Perform test-ready synthesis
  • Verify the logic equivalence of a synthesized netlist compared to an RTL design
  • Write DC-Tcl scripts to constrain designs, and run synthesis
  • Generate and interpret timing, constraint, and other debugging reports
  • Understand the effect that RTL coding style can have on synthesis results
  • Generate output data (netlist, constraints, scan-def) that works with downstream physical design or layout tools

Course Outline

Unit 1
  • Introduction to Synthesis
  • Design and Technology Data
  • Design and Library Objects
  • Timing Constraints

Unit 2
  • Environmental Attributes
  • Synthesis Optimization Techniques
  • Timing Analysis

Unit 3
  • Additional Constraint Options
  • Multiple Clocks and Timing Exceptions
  • Congestion Analysis and Optimization
  • Post-Synthesis Output Data
  • Conclusion



第二階段 Design Compiler 2: Low Power

Overview
At the end of this one day, seminar based, workshop you will understand how to apply both traditional and UPF based power optimization techniques during RTL synthesis and scan insertion:

For single voltage designs, you will learn how to apply the 2 traditional power optimization techniques of clock gating and leakage power recovery, optimizing for dynamic power and leakage power respectively.

For multi-voltage or multi-supply designs, you will learn how to apply the IEEE 1801 UPF flow that uses a power intent specification which is applied to RTL designs. You will understand how to synthesize RTL designs for the required power intent and power-optimization requirements using top-down vs. hierarchical UPF methodologies. You will also learn how to insert scan chains to the synthesized netlist ensure that the gate level design does not have any multi-voltage violations, before writing out design data for Place and Route.

Objectives

At the end of this workshop the student should be able to:

  • Apply clock gating to a design at the RTL and gate level
  • Perform multi-stage, hierarchical, and power driven clock gating
  • Perform leakage optimization using multi Vt libraries
  • Restrict the usage of leaky cells
  • Specify power intent using UPF
  • Demonstrate flexible isolation strategy in UPF 2.0
  • Check for UPF readiness of library, reporting PG pins
  • State the purpose of SCMR attribute in library
  • Recognize tradeoff when using dual vs. single rail special cells
  • Correctly specify PVT requirements
  • State how the 6 special cells are synthesized
  • Describe supply net aware Always on Synthesis
  • Apply 2 key debugging commands in a UPF flow
  • Control voltage, power domain mixing when inserting scan chains
  • Allow/prevent the reuse of level shifters and isolation cells between scan and functional paths
  • Minimize toggle in functional logic during scan shifting
  • Validate SCANDEF information for place and route

Course Outline

  • Clock Gating
  • Leakage Power Optimization
  • Power Intent using IEEE 1801 UPF
  • Library Requirements
  • Synthesis with UPF
  • Power Aware DFT



第三階段 DFT Compiler

Overview
In this workshop you will learn to use DFT Compiler to perform RTL and gate-level DFT rule checks, fix DFT DRC rule violations, and to insert scan using top-down and bottom-up flows. The workshop explores essential techniques to support large, multi-million gate SOC designs including the bottom-up scan insertion flow in the logical (Design Compiler) domain. Techniques learned include: performing scan insertion in a top-down flow; meeting scan requirements for number of scan chains, maximum chain length and reusing functional pins for scan testing, inserting an On-Chip Clocking (OCC) controller for At-Speed testing using internal clocks; and using Adaptive Scan (DFTMAX) to insert additional DFT hardware to reduce the test time and the test data volume required for a given fault coverage.

Objectives
At the end of this workshop the student should be able to:
  • Create a test protocol for a design and customize the initialization sequence, if needed, to prepare for DFT DRC checks
  • Perform DFT DRC checks at the RTL, pre-DFT, and post-DFT stages
  • Recognize common design constructs that cause typical DFT violations
  • Automatically correct certain DFT violations at the gate level using AutoFix
  • Implement top-down scan insertion flow achieving well-balanced scan chains
  • Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and Place & Route
  • Develop a bottom-up scan insertion script for full gate-level designs to use Test Models at the top-level to improve capacity and runtime
  • Insert an On-Chip Clocking (OCC) controller to use for At-Speed testing with internal clocks
  • Modify a scan insertion script to include DFT-MAX Adaptive Scan compression

Course Outline

Unit 1
  • Introduction to Scan Testing
  • DFT Compiler Flows and Setup
  • Test Protocol
  • DFT Design Rule Checks

Unit 2
  • DFT DRC GUI Debug
  • DRC Fixing
  • Top-Down Scan Insertion
  • Exporting Files

Unit 3
  • High Capacity DFT Flows
  • On-Chip Clocking (OCC)
  • Multi-Mode DFT
  • DFT MAX

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